A phase-locked loop (PLL) is a closed loop frequency control system. Its function is based on the phase sensitive detection of a phase difference between the input and output signals of a voltage controlled oscillator (VCO). They can be configured as frequency multipliers, demodulators, tracking generators or clock recovery circuits. PLLs are widely used in modern circuit design, especially in communication system design.
When data comes in, the data is reflected as logic highs or logic lows. The data receiving logic detects the logic highs or logic lows and therefore decides what the data is. When the data changes from a logic high or logic low, a data transition occurs. The data receiving logic, however, cannot detect data right at the time the transition occurs since the data is not yet stable and errors can occur even if the data is detected not at but very close to the data transition point.
Conventionally, the data is captured in flip-flops and used at the rising edge of the system clock. FIG. 1 illustrates a schema of the received data 4 with respect to the system clock 2. Line 2 illustrates the system clock. Graph 4 illustrates the data transition on the node, where points 6, 8 and 10 are data transition points. Setup time TSU and hold time TH describe the timing requirements on the flip-flop with respect to the clock 2. Setup time TSU is the time that the data must be valid before the flip-flop samples at the system clock time 7. Hold time TH is the time that data must be maintained valid after the flip-flop samples at the system clock time 7. Setup time TSU and hold time TH define a window of time that the data must be valid and stable in order to assure valid data sampling. If the setup time TSU is too close to the system clock time 7, there is no adequate setup time. If the hold time TH is too close to the system clock 7, there is no adequate hold time. The relative position of the data transition points 6, 8, and 10 with respect to the system clock time 7, is determined by the round trip latency time of the system. Also, there are variations caused by process, temperature and voltage so that the data transition points 6, 8 and 10 shift to the left or right.
If a PLL is not used, such a method should accommodate the maximum possible variation to guarantee the setup and hold time so that the circuit does not fail. A significant limitation of a non-PLL based design is that its speed is limited by the round trip latency time of the system. Since a non-PLL based design captures data from outside, using an internal or reflected clock, typically, the highest frequency of such a system not using a PLL cannot exceed 1/(latency_time), where the latency_time is the round trip latency time. For example, a system with 10 ns round trip latency time has a maximum speed of 100 MHz, and a system with 12.5 ns latency time can not be run over 80 MHz. If the IO delay is large, or the remote system is an old and slow system, the round trip latency time will be big so that the system speed will be significantly limited. The overall system speed is limited by the total latency time regardless of the speed of each component in the system. If a system has two devices, both can work at 200 MHz, but the latency time on board is 10 ns, the highest frequency of the system is 100 MHz.
Another method is the use of a PLL based design. This method solves the round trip latency issues, but incurs other costs. 1) The PLL itself is an analog circuit that must be customized for the process to operate reliably across the process variability. 2) If the PLL is used to extract the clock from the data, an encoding of the data must guarantee a minimum transition density to ensure that the sample point does not drift prior to the next changing sample. 3) Another disadvantage of a PLL is that a FIFO (First in First out buffer) is needed. Therefore the system becomes more complicated. If a system A is used to handle the data captured by a PLL and the clock coming out of the PLL that is used for capturing the data is unknown respect to system A's clock, there is no phase relationship between system A's clock and PLL's clock. A FIFO is then required between the PLL's clock domain and system A's domain to bring the data back. The data has to be stored in FIFO with respect to its own clock, and the data may need to stay in the FIFO for 3 or 4 data clocks or even more. Only after the data stored in FIFO gets synchronized across to system A's clock domain can it be emptied. The round trip latency time determines how many cells in the FIFO are required to guarantee that the data is not lost because of variations. The extra FIFO not only increases the cost, it also increases the design complexity.
The system latency time is affected by variations so that it is not a fixed value. There are three variations, namely process (the process of fabricating the semiconductor circuit) variation, temperature variation and voltage variation. Among the three, the variation caused by the process is typically the greatest. However, the process variation is a fixed value after a circuit has been built. The voltage and temperature variations are not fixed. They may change depending on the local conditions. Normally, they change relatively slowly over time.
With the above-discussed limitations of the PLL and non-PLL based designs, the system's data receiving speed is greatly limited. Therefore, an alternative technology that overcomes these limitations is needed.